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1 ? fn3116.7 DG406, dg407 single 16-channel/differ ential 8-channel, cmos analog multiplexers the DG406 and dg407 monolithic cmos analog multiplexers are drop-in replacements for the popular dg506a and dg507a series devices. they each include an array of sixteen analog switches, a ttl and cmos compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. these multiplexers feature lower signal on resistance (<100 ? ) and faster transition time (t trans < 300ns) compared to the dg506a and dg507a. charge injection has been reduced, simplifying sample and hold applications. the improvements in the DG406 series are made possible by using a high voltage silicon -gate process. an epitaxial layer prevents the latch-up associated with older cmos technologies. the 44v maximum voltage range permits controlling 30v p-p signals when operating with 15v power supplies. the sixteen switches are bilateral, equally matched for ac or bidirectional signals. the on resistance variation with analog signals is quite low over a 5v analog input range. pinouts features ? on-resistance (max). . . . . . . . . . . . . . . . . . . . . . . . 100 ? ? low power consumption (p d ) . . . . . . . . . . . . . . . <1.2mw ? fast transition time (max) . . . . . . . . . . . . . . . . . . . 300ns ? low charge injection ? ttl, cmos compatible ? single or split supply operation applications ? battery operated systems ? data acquisition ? medical instrumentation ? hi-rel systems ? communication systems ? automatic test equipment related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? v+ nc nc s 16 s 15 s 14 s 13 s 12 s 11 s 10 s 9 gnd nc a 3 d s 8 s 7 s 6 s 5 s 3 s 1 en a 0 a 1 a 2 v- s 4 s 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v+ d b nc s 8b s 7b s 6b s 5b s 4b s 3b s 2b s 1b gnd nc nc d a s 8 a s 7 a s 6 a s 5 a s 3 a s 1 a en a 0 a 1 a 2 v- s 4 a s 2 a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DG406 (pdip, soic) top view dg407 (pdip, soic) top view ordering information part number temp. range ( o c) package pkg. dwg. #. DG406dj -40 to 85 28 ld pdip e28.6 DG406dy -40 to 85 28 ld soic m28.3 dg407dj -40 to 85 28 ld pdip e28.6 dg407dy -40 to 85 28 ld soic m28.3 data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 schematic diagram (typical channel) v+ gnd a 0 a x en v- v ref level shift decode/ drive v+ v+ v- d s 1 s n functional diagrams DG406 dg407 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 d to decoder logic controlling both tiers of muxing address decoder 1 of 16 enable a 0 a 1 a 2 a 3 en s 2a s 3a s 4a s 5a s 6a s 7a s 8a s 1b s 2b s 3b s 4b s 5b s 6b s 7b s 8b d a to decoder logic controlling both tiers of muxing address decoder 1 of 8 enable a 0 a 1 a 2 en s 1a d b DG406, dg407
3 DG406 truth table a 3 a 2 a 1 a 0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 dg407 truth table a 2 a 1 a 0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 logic ?0? = v al < 0.8v. logic ?1? = v ah > 2.4v. x = don?t care. DG406, dg407
4 absolute m aximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0v gnd to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v digital inputs, v s , v d (note 1). . . . . . (v-) -2v to (v+) +2v or 20ma, whichever occurs first continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . 30ma peak current, s or d (pulsed 1ms, 10% duty cycle max) . . . . . 100ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc and soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. 2. signals on s x , d x , en or a x exceeding v+ or v- are clamped by internal diodes . limit diode current to maximum current ratings. electrical specifications test conditions: v+ = +15v, v- = -15v, v al = 0.8v, v ah = 2.4v unless otherwise specified parameter test conditions temp ( o c) (note 3) min (note 4) typ (note 3) max units dynamic characteristics transition time, t trans (see figure 1) 25 - 200 300 ns full - - 400 ns break-before-make interval, t open (see figure 3) 25 25 50 - ns full 10 - - ns enable turn-on time, t on(en) (see figure 2) 25 - 150 200 ns full - - 400 ns enable turn-off time, t off(en) 25 - 70 150 ns full - - 300 ns charge injection, q c l = 1nf, v s = 0v, r s = 0 ? 25 - 40 - pc off isolation, oirr v en = 0v, r l = 1k ? , f = 100khz (note 7) 25 - -69 - db logic input capacitance, c in f = 1mhz 25 - 7 - pf source off capacitance, c s(off) v en = 0v, v s = 0v, f = 1mhz 25 - 8 - pf drain off capacitance, c d(off) v en = 0v, v d = 0v, f = 1mhz DG406 25 - 160 - pf dg407 25 - 80 - pf drain on capacitance, c d(on) v en = 5v, v d = 0v, f = 1mhz DG406 25 - 180 - pf dg407 25 - 90 - pf digital input characteristics logic high input voltage, v inh full 2.4 - - v logic low input voltage, v inl full - - 0.8 v logic high input current, i ah v a = 2.4v, 15v full -1 - 1 a logic low input current, i al v en = 0v, 2.4v, v a = 0v full -1 - 1 a analog switch characteristics drain-source on resistance, r ds(on) v d = 10v, i s = + 10ma (note 5) 25 - 50 100 ? full - - 125 ? r ds(on) matching between channels, ? r ds(on) v d = 10v, -10v (note 6) 25 - 5 - % DG406, dg407
5 source off leakage current, i s(off) v en = 0v, v s = 10v, v d = + 10v 25 -0.5 0.01 0.5 na full -5 - 5 na drain off leakage current, i d(off) DG406 25 -1 0.04 1 na full -40 - 40 na dg407 25 -1 0.04 1 na full -20 - 20 na drain on leakage current, i d(on) v s = v d = 10v (note 5) DG406 25 -1 0.04 1 na full -40 - 40 na dg407 25 -1 0.04 1 na full -20 - 20 na power supply characteristics positive supply current, i+ v en = v a = 0v or 5v (standby) 25 - 13 30 a full - - 75 a negative supply current, i- 25 -1 -0.01 - a full -10 - - a positive supply current, i+ v en = 2.4v, v a = 0v (enabled) 25 - 80 100 a full - - 200 a negative supply current, i- 25 -1 -0.01 - a full -10 - - a electrical specifications single supply test conditions: v+ = 12v, v- = 0v, v al = 0.8v, v ah = 2.4v, unless otherwise specified parameter test conditions temp ( o c) (note 3) min (note 4) typ (note 3) max units dynamic characteristics switching time of multiplexer, t trans v s1 = 8v, v s8 = 0v, v in = 2.4v 25 - 300 450 ns enable turn-on time, t on(en) v inh = 2.4v, v inl = 0v, v s1 = 5v 25 - 250 600 ns enable turn-off time, t off(en) 25 - 150 300 ns charge injection, q c l = 1nf, v s = 6v, r s = 0 ? 25 - 20 - pc electrical specifications test conditions: v+ = +15v, v- = -15v, v al = 0.8v, v ah = 2.4v unless otherwise specified (continued) parameter test conditions temp ( o c) (note 3) min (note 4) typ (note 3) max units DG406, dg407
6 analog switch characteristics analog signal range, v analog full 0 - 12 v drain-source on-resistance, r ds(on) v d = 3v, 10v, i s = -1ma (note 5) 25 - 90 120 ? r ds(on) matching between channels (note 6), ? r ds(on) 25 - 5 - % source off leakage current, i s(off) v en = 0v, v d = 10v or 0.5v, v s = 0.5v or 10v 25 - 0.01 - na drain off leakage current, i d(off) DG406 25 - 0.04 - na dg407 25 - 0.04 - na drain on leakage current, i d(on) v s = v d = 10v (note 5) DG406 25 - 0.04 - na dg407 25 - 0.04 - na power supply characteristics positive supply current (i+) (standby) v en = 0v or 5v, v a = 0v or 5v 25 - 13 30 a full - 13 75 a negative supply current (i-) (enabled) 25 -1 -0.01 - a full -5 -0.01 - a notes: 3. the algebraic convention whereby the most negati ve value is a minimum and the most posit ive a maximum, is used in this data she et. 4. typical values are for design aid only, not guaranteed nor production tested. 5. sequence each switch on. 6. ? r ds(on) = (r ds(on) (max) - r ds(on) (min)) r ds(on) average. 7. worst case isolation occurs on channel 8b due to proximity to the drain pin. test circuits and waveforms figure 1a. DG406 test circuit figure 1b. dg407 test circuit electrical specifications single supply test conditions: v+ = 12v, v- = 0v, v al = 0.8v, v ah = 2.4v, unless otherwise specified (continued) parameter test conditions temp ( o c) (note 3) min (note 4) typ (note 3) max units en a3 DG406 gnd a 2 a 1 s 1 s 2 - s 15 s 16 d v- v+ 10v v o 35pf 300 ? 50 ? +15v +2.4v -15v a 0 10v logic input en a 0 dg407 gnd a 1 a 2 s 1b ? s 8b d b v- v+ 10v v o 35pf 300 ? 50 ? +15v +2.4v -15v ? = s 1a - s 8a , s 2b - s 7b , d a 10v logic input DG406, dg407
7 figure 1c. measurement points figure 1. transition time figure 2a. DG406 test circuit figure 2b. dg407 test circuit figure 2c. measurement points figure 2. enable switching times figure 3a. test circuit figure 3b. measurement points figure 3. break-before-make interval test circuits and waveforms (continued) logic input switch output v o 3v v s1b 50% t r < 20ns t f < 20ns t trans 50% 0v 0v v s8b t trans s 8 on 80% 80% s 1 on v s8 v s1 en a3 DG406 gnd a 2 a 1 s 1 s 2 - s 16 d v- v+ -5v v o 35pf 300 ? 50 ? +15v -15v a 0 logic input v in en a 0 dg407 gnd a 1 a 2 s 1b ? d a and d b v- v+ -5v v o 35pf 300 ? 50 ? +15v -15v ? = s 1a - s 8a , s 2b - s 8b , d a logic input v in logic input switch output v o 3v v o 50% t r < 20ns t f < 20ns t on(en) 0v 50% t off(en) 90% 0v v in v o en a3 DG406 gnd a 2 a 1 all s d, v- v+ +5v (v s ) v o 35pf 300 ? 50 ? +15v +2.4v -15v a 0 dg407 and d a d b logic input logic input switch output v o 3v v s t r < 20ns t f < 20ns t open 0v 0v 80% DG406, dg407
8 typical performance curves figure 4. r ds(on) vs v d and supply figure 5. r ds(on) vs v d and temperature figure 6. r ds(on) vs v d and supply figure 7. i d , i s leakage currents vs analog voltage figure 8. i d , i s leakage vs temperature figure 9. switching times vs bipolar supplies 5v 8v 10v 12v 15v 20v 160 140 120 100 80 60 40 20 0 -20 -16 -12 -8 -4 0 4 8 12 16 20 v d , drain voltage (v) r ds(on) , on resistance ( ? ) 125 o c -40 o c -55 o c 25 o c 85 o c 0 o c v+ = 15v v- = -15v 80 70 60 50 40 30 20 10 0 -15 -10 -5 5 10 015 v d , drain voltage (v) r ds(on) , on-resistance ( ? ) v- = 0v v+ = 7.5v 10v 12v 15v 20v 22v 240 200 160 120 80 40 0 048121620 v d , drain voltage (v) r ds(on) , on-resistance ( ? ) -10 -5 5 10 015 v s , v d , source drain voltage (v) v+ = 15v, v- = -15v v s = -v d for i d(off) v d = v s(open) for i d(on) i s(off) DG406 i d(on) , i d(off) -15 120 80 40 0 -40 -80 -120 i d , i s , current (pa) dg407 i d(on) , i d(off) v+ = 15v, v- = -15v v s or v d = 10v i s(off) i d(on) , i d(off) 100na 10na 1na 100pa 10pa 1pa 0.1pa i d , i s , current (a) -55 -35 -15 5 25 45 65 85 105 125 temperature ( o c) 350 300 250 200 150 100 50 0 5101520 v supply , supply voltage ( v) time (ns) t trans t on(en) t off(en) DG406, dg407
9 figure 10. switching times vs single supply figure 11. off isolation vs frequency figure 12. supply currents vs switching frequency figure 13. t on / t off vs temperature figure 14. switching threshold vs supply voltage typical performance curves (continued) 700 600 500 400 300 200 100 0 5101520 v+, supply voltage (v) time (ns) t trans t on(en) t off(en) v- = 0v 1k 10k 1m 100k 10m f, frequency (hz) 100 -140 -120 -100 -80 -60 -40 -20 isol (db) 0 100 1k 100k 1m 10k 10m f, frequency (hz) e n = 5v, a x = 0v or 5v i gnd 10 10 8 6 0 -4 -8 -10 i, current (ma) i+ i- 4 2 -2 -6 300 280 260 240 220 200 140 120 60 -55 -35 -15 5 25 45 65 85 105 125 temperature ( o c) time (ns) 180 160 100 80 t trans t on(en) t off(en) v+ = 15v, v- = -15v 5101520 v supply , supply voltage ( v) 0 0 1 2 3 v a ,(v) DG406, dg407
10 die characteristics die dimensions: 2490 m x 4560 m x 485 m metallization: type: sial thickness: 12k ? 1k ? passivation: type: nitride thickness: 8k ? 1k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout DG406 v- s 16 d nc v+ s 5 a 0 en s 7 s 6 s 5 s 4 s 3 s 2 s 1 a 1 a 2 a 3 gnd s 15 s 14 s 13 s 12 s 11 s 10 s 9 DG406, dg407
11 DG406, dg407 die characteristics die dimensions: 2490 m x 4560 m x 485 m metallization: type: sial thickness: 12k ? 1k ? passivation: type: nitride thickness: 8k ? 1k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout dg407 a 0 en a 1 a 2 nc gnd s 8a s 7a s 6a s 5a s 4a s 3a s 2a s 1a v- d a d b v+ s 8b s 7b s 6b s 5b s 4b s 3b s 2b s 1b
12 DG406, dg407 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with th e leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com DG406, dg407 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93

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